The present invention relates generally to a semiconductor package, and more particularly, to a semiconductor package having a high density and a high capacity.
In the semiconductor industry, packaging technologies for integrated circuits have continuously been developed to satisfy the demand toward miniaturization and mounting reliability. For is example, the demand toward miniaturization has expedited the development of techniques for a package with a size approaching that of a chip, and the demand toward improved mounting reliability has highlighted the importance of packaging techniques for improving the efficiency of mounting work and mechanical and electrical reliability after mounting.
As the demand for miniaturization and high performance in electric and electronic products continues, various techniques for providing a semiconductor package of high capacity have been researched and developed. A method for providing a semiconductor package of high capacity includes the high integration of a memory chip. Such high integration can be realized by integrating an increased number of cells in a limited space of a semiconductor chip.
However, the high integration of a memory chip requires high precision techniques, such as a fine line width, and a lengthy development period. Under these situations, a stacking technique has been suggested as another method for providing a semiconductor package of high capacity.
The stacking technique is includes a method of embedding to two stacked chips in one package and a method of stacking two separate packages which are independently packaged. The method of stacking two separate packages increases the thickness of the entire semiconductor package and therefore cannot accommodate the trend toward miniaturization of electric and electronic products.
Therefore, research has been actively conducted for a stack package or a multi-chip package in which two or three semiconductor chips are mounted in one package.
However, in the conventional art, metal wires are used to electrically connect a substrate and respective stacked semiconductor chips, and this leads to several problems which are detailed below.
First, when conducting a wire bonding process for the substrate and the respective semiconductor chips stacked on the substrate using the metal wires, the lengths of the metal wires increase as the number of semiconductor chips increases, and therefore, the metal wires are likely to be short-circuited due to a sweeping phenomenon of the metal wires during a molding process.
Second, as the height of the stacked semiconductor chips increases, the lengths of the metal wires increase and thus, it is difficult to properly transmit electrical signals. Further, cracks are likely to occur in the semiconductor chips due to stresses induced by wire bonding.
Third, in order to conduct wire bonding for the substrate and the respective stacked semiconductor chips on both sides of the semiconductor chips by using the metal wires, mold margins should be secured on both sides of the semiconductor chips. Due to this fact, the size of the semiconductor package is likely to increase.